Verilog Hardware Quine

This is my take on the "Hardware Quine" problem:

A chip design that outputs its own HDL source!

See this post for further info.

Getting Started

Get the code here

The design should be able to run on any FPGA.

In the current state it is tuned to run on the iCEBreaker board (Lattice iCE40 UP5K).

It runs on the iCEBreaker's 12 MHz clock frequency
It outputs to asynchronous serial, 230400 8N1

To start a test of the quine in simulation, run

make swcheck

To start a test of the quine in hardware, run

make hwcheck

This requires exactly one (1) iCEBreaker board to be connected to the PC.

The makefile has a PORT parameter to specify the serial port if it is not at /dev/ttyUSB1.

Both checks can be run using

make all

About the Design

The design can be found in vquinefsm.v or here:

module q#(parameter Q=50,U=37,I=498)(input N,output E);reg [I*8-1:0]q={"
module q#(parameter Q=50,U=37,I=498)(input N,output E);reg [I*8-1:0]q={%
,8'b0};assign E=e;reg e=1;reg [3:0]b=9,s=1;reg [7:0]p=Q,r=0,o;reg [8:0]c
=I-1,k=0;always @(posedge N)begin o<=q[c*8+:7]; p<=p[7]?Q:p-1;if(p[7]&&s
)begin b<=b-1;if(b==9)begin e<=0;c<=c-1;r<=o;if(s==1&&o==U)begin k<=c-1;
s<=2;r<=34;c<=I-1;end else if(s==2&&!o)begin s<=3;c<=k;r<=34;end else if
(s==3&&!o)begin s<=4;r<=10;end else if(s==4)begin s<=0;e<=1;end end else
 if(!b)begin;e<=1;b<=9;end else {r,e}<={1'b0,r};end end endmodule",8'b0}
;assign E=e;reg e=1;reg [3:0]b=9,s=1;reg [7:0]p=Q,r=0,o;reg [8:0]c=I-1,k
=0;always @(posedge N)begin o<=q[c*8+:7]; p<=p[7]?Q:p-1;if(p[7]&&s)begin
 b<=b-1;if(b==9)begin e<=0;c<=c-1;r<=o;if(s==1&&o==U)begin k<=c-1;s<=2;r
<=34;c<=I-1;end else if(s==2&&!o)begin s<=3;c<=k;r<=34;end else if(s==3&
&!o)begin s<=4;r<=10;end else if(s==4)begin s<=0;e<=1;end end else if(!b
)begin;e<=1;b<=9;end else {r,e}<={1'b0,r};end end endmodule

Nothing really that special or clever, just a "data" and a "printer" portion.

It takes up about 500 LCs on iCE40 (so, ~10% of UP5K), so there's definitely room for improvement.

However, compared to the smaller (130 LEs) solution here, this solution...

can be used with common serial ports and
does not require any pre-processing (a special DEC SIXBIT encoding is used in the smaller solution).

My solution, synthesized with yosys using synth_intel -family cycloneiv uses 534 "cells".

Main Page